The escalating requirements for high density and performance associated with ultra large scale integration demand design features of 0.25 microns and under, e.g., about 0.18 microns, increased transistor and circuit speeds, and high reliability. These requirements challenge the limitations of semiconductor technology.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etchback step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically doped moncrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer is deposited on the first dielectric layer. The metal layer is typically a composite comprising a first metal layer such as tungsten or titanium, a second intermediate primary layer such as aluminum or an aluminum alloy, and an upper anti-reflective coating, which also serves as an etchstop layer, such as titanium nitride. A photoresist mask is formed on the metal layer having a pattern defining a plurality of conductive features in accordance with design requirements. The metal layer is etched, using the photoresist mask, to form a conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer, such as spin-on glass (SOG), is then applied to the resulting conductive pattern to fill the gaps. Another dielectric layer is deposited, such as silicon oxide derived from tetraethyl orthosilicate (TEOS) or silane by plasma enhanced chemical vapor deposition (PECVD). Planarization is then effected, as by etching or chemical mechanical polishing (CMP).
The conductive pattern typically comprises a dense array of metal features, typically separated by gaps less than about 1 micron, e.g., about 0.375 microns for metal features of about 0.50 microns. Such a dense array is schematically illustrated in FIG. 1, and comprises leading metal feature 11A and trailing metal feature 11B formed on first dielectric layer 10. A layer of gap filling material 12, such as SOG, is deposited to fill in the gaps. A preferred gap filling material is hydrogen silsesquioxane (HSQ).
However, it was found that when a dense array is bordered by an open field, i.e., a distance extending beyond about 1 micron, such as beyond about 1.5 microns, e.g., greater than 2 microns, cracking occurs in the dielectric gap fill layer 12 proximate leading 11A and trailing 11B metal features bordering the open field, as indicated by reference numeral 13. Such cracking typically occurs where the gap filling layer is deposited at a relatively high thickness and at a relatively severe angle, as where a leading or trailing metal feature borders an open field. Such cracks adversely impact circuit speeds and device reliability.
Accordingly, there exists a need for semiconductor methodology for gap filling patterned metal layers without experiencing cracking in high stress areas, such as adjacent leading and trailing edges of a dense array bordering an open field.